NextGArch Lab
Pioneering the Future of NextGen Systems and Networks!
At the University of Michigan, NextGArch Lab is dedicated to revolutionizing computer systems, networks, and architectures through cutting-edge research and innovation in CSE and EECS.
About NextGArch Lab
Our Mission
At the NextGArch Lab, we conduct innovative research in computer systems, networks, and architectures. Our work involves developing domain-specific abstractions, compilers, and architectures for networks and systems, with applications in AI/ML, self-driving networks, cloud/edge computing, and 5G/6G.
Research Areas
Domain-Specific Systems
New programming models, runtime systems, and architectures for nextgen high-performance and scalable computing.
Domain-Specific Networks
Novel networking protocols, architectures, and algorithms for efficient and reliable data communication.
Domain-Specific Architectures
Innovative architectures for future computing systems, including hw/sw co-design and accelerators for line-rate and proficient ML/AI.
Systems+X and Networks+X
Leveraging cross-domain insights—e.g., X = ML/AI—to push the boundaries of efficiency, scalability, and innovation in distributed and networked systems.
Latest News
Mar 19, 2026
Murayyiam did a fantastic job presenting SpliDT at P4 Dev Day!

LinkedIn

🗓️ TOMORROW: March 19 at 11 am ET/4 pm CET ✨ P4 Developer Day || SpliDT: Partitioned Decision Trees for Scalable Stateful Inference at Line Rate with Murayyiam Parvez 🎟️ Register here:… | P4 Langua

🗓️ TOMORROW: March 19 at 11 am ET/4 pm CET ✨ P4 Developer Day || SpliDT: Partitioned Decision Trees for Scalable Stateful Inference at Line Rate with Murayyiam Parvez 🎟️ Register here: https://lnkd.in/dMZWEVBj Abstract: Machine learning is increasingly used in programmable data planes, such as switches and smartNICs, to enable real-time traffic analysis and security monitoring at line rate. Decision trees (DTs) are particularly well-suited for these tasks due to their interpretability and co

Mar 18, 2026
Woohoo! The NextGArch Lab is on a roll—celebrating its second PhD graduate stepping into the real world. Huge congratulations to the outstanding Dr. Annus Zulfiqar!
Mar 8, 2026
Our own, Venkat Kunaparaju, is joining NVIDIA to work on all things networking (for AI and Cloud Gaming). Congratualtion, Venkat!

LinkedIn

Huge congratulations, Venkat Kunaparaju! 🎉 It has been a pleasure having you as part of our NextGArch Lab since 2023 ... quickly standing out for your initiative, technical depth, and ability to… |

Huge congratulations, Venkat Kunaparaju! 🎉 It has been a pleasure having you as part of our NextGArch Lab since 2023 ... quickly standing out for your initiative, technical depth, and ability to turn ideas into real systems work. Your contributions to our GigaFlow work on scalable fast paths for Open vSwitch and SmartNICs have been outstanding—presenting it at TechCon and then taking it through HotCHIPs and ASPLOS! 🙏 For an undergraduate student to contribute at this level—across architect

Mar 4, 2026
Prof. Shahbaz recognized as a Michigan Housing Honored Instructor. Congratulations!

Michigan Housing

Michigan Housing Honored Instructors

Since 2018, Michigan Housing has provided residential students an opportunity to honor the instructors who make a positive impact on their collegiate journey at the University of Michigan. Michigan Housing is excited to continue to celebrate the incredible faculty and instructors that inspire our students each and every day.

Feb 3, 2026
Many congratulations to Marilyn Rego on being inducted into Tau Beta Pi, The Engineering Honor Society!

www.tbp.org

Tau Beta Pi - The Engineering Honor Society

Homepage for Tau Beta Pi members including recent news, upcoming events, and useful links for officers and general members.

Jan 29, 2026
Ertza will be presenting our recent work on OptiNIC at the OCP's Time Appliances Project (TAP).

linkedin

For our next OCPTAP session, we have Ertza Warraich, systems and networking researcher and recent Ph.D. graduate from Purdue University. Ertza will present OptiNIC, a domain-specific RDMA transport… |

For our next OCPTAP session, we have Ertza Warraich, systems and networking researcher and recent Ph.D. graduate from Purdue University. Ertza will present OptiNIC, a domain-specific RDMA transport designed for large-scale distributed machine learning. His talk explores how relaxing traditional reliability and in-order delivery guarantees can dramatically reduce tail latency and improve throughput across multi-GPU, high-speed interconnects. The session will cover: • Why strict RDMA semantics be

Dec 10, 2025
SpliDT accepted to NSDI '26. Congratulations, Murayyiam Parvez, Annus Zulfiqar, and the team!

linkedin

SPLIDT Accepted to NSDI2026: Scalable Stateful Inference at Line Rate | Muhammad Shahbaz posted on the topic | LinkedIn

🚨 Big and humbling news! Our paper SPLIDT: Partitioned Decision Trees for Scalable Stateful Inference at Line Rate has been accepted to #NSDI2026! 🎉 In-network ML has long been caught between a rock and a hard place—accuracy or scalability. SPLIDT says: why not both? SPLIDT reimagines how decision trees operate in programmable data planes by: • ✂️ Partitioning trees into subtrees with their own stateful features, • 🔁 Recirculating packets to reuse registers and match-action tables (MATs) ac

Nov 25, 2025
Woo hoo! NextGArch Lab proudly celebrates its very first PhD graduate—congratulations to the one and only Dr. Ertza Warraich!
Oct 29, 2025
Celeris accepted to IEEE CAL '25. Congratulations, Ertza Warraich, Ali Imran, Annus Zulfiqar, and the team!

linkedin

How ML can transform transport: A new paper on RDMA and ML | Muhammad Shahbaz posted on the topic | LinkedIn

Transport is the next frontier in accelerating foundation models, and getting there means "Reimagining RDMA Through the Lens of ML"! In our upcoming paper in IEEE CAL'25, we explore how a domain-specific focus can supercharge transport for ML workloads. https://lnkd.in/eF4EaciF This work is being spearheaded by my daring and relentless students, Ertza Warraich, Ali Imran, and Annus Zulfiqar, along with our amazing collaborators, Shay Vargaftik and Sonia Fahmy! ACM SIGARCH | Purdue Computer Sc

Our Team
Muhammad Shahbaz
Principal Investigator (PI)
Assistant Professor, U-M (CSE)
Annus Zulfiqar
Ph.D. Student (U-M)
Focus: HW/SW Co-Design, Virtual Networks, and In-Network AI
Bilal Saleem
Ph.D. Student (Purdue)
Focus: Cloud-Native Systems, Edge Computing, and 5G
Murayyiam Parvez
Ph.D. Student (Purdue)
Focus: Network Security, In-Network ML, and Programmable Data Planes
Ali Imran
Ph.D. Student (U-M)
Focus: Programmable Data Planes, In-Network ML, and Agentic Systems
Marilyn Rego
Ph.D. Student (U-M)
Focus: Agentic Systems, In-Network ML, and Domain-Specific LLMs
Andrew Ajamian
Ph.D. Student (U-M)
Focus: Computer Systems and Architecture + ML
Qizheng Zhang
Ph.D. Student (Stanford), co-advised with Kunle Olukotun
Focus: ML and Agentic Systems, In-Network ML, and Video Streaming
Advay Singh
B.S. Student (U-M)
Focus: Cloud Computing, and ML Systems and Networks
Sruthi Shivaramakrishnan
M.S. Student (U-M)
Focus: AI and Systems
Geon Kim
B.S. Student (U-M)
Focus: Systems and Networks
Yasin Huq Shafiq
B.S. Student (U-M)
Focus: Systems and Networks
Selected Publications
NSDI '26
SpliDT: Partitioned Decision Trees for Scalable Stateful Inference at Line Rate
Murayyiam Parvez*, Annus Zulfiqar*, Roman Beltiukov, Shir Landau Feibish, Walter Willinger, Arpit Gupta, Muhammad Shahbaz (*co-primary)

33:26

YouTube

SpliDT: Partitioned Decision Trees for Scalable Stateful Inference at Line Rate || P4 Developer Day

Machine learning is increasingly used in programmable data planes, such as switches and smartNICs, to enable real-time traffic analysis and security monitoring at line rate. Decision trees (DTs) are particularly well-suited for these tasks due to their interpretability and compatibility with the Reconfigurable Match-Action Table (RMT) architecture. However, current DT implementations require collecting all features upfront, which limits scalability and accuracy due to constrained data plane reso

IEEE Computer Architecture Letters (CAL) '25
Reimagining RDMA Through the Lens of ML
Ertza Warraich, Ali Imran, Annus Zulfiqar, Shay Vargaftik, Sonia Fahmy, Muhammad Shahbaz
MICRO '25
NetSparse: In-Network Acceleration of Distributed Sparse Kernels
Gerasimos Gerogiannis, Charles Block, Dimitrios Merkouriadis, Annus Zulfiqar, Filippos Tofalos, Muhammad Shahbaz, Josep Torrellas
TECHCON '25
SpliDT: Partitioned Decision Trees for Scalable Stateful ML Inference at Line Rate
Marilyn Rego, Murayyiam Parvez, Annus Zulfiqar, Roman Beltiukov, Shir Landau Feibish, Walter Willinger, Arpit Gupta, Muhammad Shahbaz
Euro S&P '25
O'MINE: A Novel Collaborative DDoS Detection Mechanism for Programmable Data-Planes
Enkeleda Bardhi, Chenxing Ji, Ali Imran, Muhammad Shahbaz, Riccardo Lazzeretti, Mauro Conti, Fernando Kuipers
ISCA '25
HardHarvest: Hardware-Supported Core Harvesting for Microservices
Jovan Stojkovic, Chunao Liu, Muhammad Shahbaz, Josep Torrellas
ASPLOS '25
Gigaflow: Pipeline-Aware Sub-Traversal Caching for Modern SmartNICs
Annus Zulfiqar, Ali Imran, Venkat Kunaparaju, Ben Pfaff, Gianni Antichi, Muhammad Shahbaz

p4.org

Gigaflow: Pipeline-Aware Sub-Traversal Caching for Modern SmartNICs – P4 – Language Consortium

Figure 1: (a) A traversal is a complete sequence of table lookups through the vSwitch pipeline that generates a Megaflow rule. (b) A sub-traversal is a subset of these lookups within a traversal, capturing smaller, reusable segments shared across multiple flows.

Computer Science and Engineering

Streamlining cloud traffic with a Gigaflow Cache

Gigaflow improves virtual switches for programmable SmartNICs, delivering a 51% higher hit rate and 90% lower misses.

Tech Xplore

Gigaflow cache streamlines cloud traffic, with 51% higher hit rate and 90% lower misses for programmable SmartNICs

A new way to temporarily store memory, Gigaflow, helps direct heavy traffic in cloud data centers caused by AI and machine learning workloads, according to a study led by University of Michigan researchers.

15:34

YouTube

Gigaflow - Pipeline-Aware Sub-Traversal Caching for Modern SmartNICs (ASPLOS 2025)

Learn about Gigaflow: a high hit rate, SmartNIC-native cache for virtual switches (like OVS) that expands rule space coverage by two orders of magnitude and reduces cache misses by up to 90%. This work was presented as ASPLOS'25.

Our Sponsors
NSF
National Science Foundation
SRC
Semiconductor Research Corporation
Intel
Intel Corporation
Google Research
Google
Facebook
Meta
VMware Research
by Broadcom
AMD
Advanced Micro Devices
Nvidia
Nvidia Corporation
ONF
Open Networking Foundation
Contact Us
University of Michigan
Computer Science and Engineering, EECS
Location
Leinweber Computer Science and Information Building (4252), University of Michigan
Social Media
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